A main memory unit of 4 megabytes of capacity is built using 1M × 1-bit DRAM chips. Each DRAM chip has 1K cells in cells with 1K lines, and the time taken for a single refresh operation is 100 nanoseconds. What is the time required for refreshing operations on all cells in memory unit?
It was asked in the gate 2010.
Here's where I got stuck. How is this memory arranged? To obtain 1 mx 1-bit cells from 4 MB to us, we need 32 such cells. How these 32 cells are arranged to create 4 MB of memory (in particular, how they are arranged for rows and columns) I believe it is important to answer the above problem during the refresh cycle, The entire line of memory gets refreshed at one time. Any help will be very much appreciated.
Each 1m X 1 chip is organized as 1K X 1K 1 row. 4 MB storage is necessary for the construction of 32 items. But all the chips can be refreshed together. The oysters are refreshed. Then the total fresh time is 100 * 2 ^ 10 ns
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